| 摘要 |
PURPOSE:To speed up the reading by detecting the voltage drop of a bit line with a single transistor, discharging a bit line through a single transistor to shorten a detecting time and reduce resistance at the time of discharging. CONSTITUTION:While a pre-charge control line 11 is kept in a L-level for a prescribed period, respective bit lines b0-bm are charged (pre-charged) by a power source voltage VCC. Thereafter, the inverse read enable signal of L-level is supplied to a terminal 14, and at the same time, the read control signal of H-level is supplied to either one of read control lines w0-wn. The voltage of the bit line b0 drops because of its gradual discharging through an FETQb. When the voltage between gate and source of the FETQ10 of a sense amplifier circuit 13 connected to the bit line b0 exceeds a threshold voltage, the FETQ10 detects the voltage drop of the bit line b0, and turns to be conductive. After the discharging of such as read control line w0 is ended, an output signal 12 reads the levels of respective bit lines b0-bm through terminals a0-am, and outputs the result to a circuit in the following stage.
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