| 摘要 |
PURPOSE:To eliminate the need for the change in the design of a read circuit even with different read size and to simplify a constitution reducing a picture data by selecting an output signal in a dummy bit elimination circuit in response to the dummy bit number of a solid-state image pickup device and outputting a signal while removing the dummy output signal. CONSTITUTION:A read clock signal RCLK is fed to a frequency division circuit 10 and a CCD timing generation circuit 20 externally and a signal 4RCLK being 1/4 frequency division by the frequency division circuit 10 synchronized the entire circuit. When a synchronizing signal is inputted, the circuit 20, a dummy bit counter/decoder circuit 30 and an ENADMA circuit 40 are initialized and a decoder output is selected and fed to a dummy bit control to discriminate the dummy output and the signal output existing in the CCD output signal. The output of the decoder 30 is obtained by counting the 4RCLK. The output is detected externally, a unmagnification/reduction signal is outputted and 8 clocks are inputted to a byte counter circuit 50. The byte counter output and the decoder output are inputted to an AND circuit 51 to set the circuit 40 thereby attaining a DMA request.
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