| 摘要 |
PURPOSE:To attain high speed logic operation even when driving a large load by obtaining two inputs (false/true) of a push-pull buffer circuit from an output of an SCFL circuit. CONSTITUTION:When an input signal, comparison voltage are inputted respectively to input terminals 60, 61, the difference between the input signal and the comparison voltage is amplified and appears at output terminals 20, 21 of a souce coupling type logic circuit (SCFL circuit). Output terminal 20, 21 of the SCFL circuit are connected to gates of MESFETs 80, 81 of a buffer circuit to turn on either MESFET and to turn off the other. Thus, an output is obtained from the output terminal 30. Assuming a low level at a node 21 as VOL, an output voltage of the terminal 30 as Vout and a threshold voltage of the FET 81 as VT, and they satisfy the condition of VOL-VT<Vout, then the FET 81 is acted within the drain current saturation region and the high speed logic operation is attained. |
