发明名称 |
SYMBOLIC PROCESSING SYSTEM AND METHOD |
摘要 |
In a symbolic processing system having a microprogrammable processor, the processor includes a plurality of gate arrays implementing a date path circuit and sources and destinations for data from the data path circuit. The gate arrays are connected by an internal bus and the internal bus is utilized as a first bus during a first portion of a clock cycle to enable the data path circuit to receive data from one of different sources and utilizing internal bus as a second bus during a second nonoverlapping portion of the clock cycle to apply the result of an operation to one of different destinations in the processor. In this way a single bus is time multiplexed. |
申请公布号 |
JPS62251829(A) |
申请公布日期 |
1987.11.02 |
申请号 |
JP19870092940 |
申请日期 |
1987.04.15 |
申请人 |
SHINBORITSUKUSU INC |
发明人 |
BURUUSU II EDOWAAZU;RONARUDO JIEI REBERU |
分类号 |
G06F9/44;G06F7/00;G06F9/22;G06F13/42;G06F15/78 |
主分类号 |
G06F9/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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