| 摘要 |
PURPOSE:To generate a signal in the full cycle of a clock pulse, by holding a voltage generated in the half cycle of the clock pulse, in the remaining half cycle. CONSTITUTION:When a clock is switched, and a clock 5a goes to an H, a pair of transistors 8A and 8B are operated, and differential amplification is performed, and furthermore, a transistor 19B is turned on, and a transistor 19A is turned off, thereby, the base potential of a transistor 15 is lowered, however, a current to operate the transistor 15 is supplied, thereby, the voltage of a holding capacitance 20 can be remained as it is. Furthermore, by switching the clock, the transistor 19A is turned on when the base voltage of the transistor 15 is at an L level, and it is reset to the L level by discharging the charge of the holding capacitance 20 by the current of a current source 16. Thereby, a converted output generates the data almost equal to one period of the clock.
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