| 摘要 |
PURPOSE:To attain stable PLL operation without the need for a differentiation circuit by using a phase error detection pulse so as to divide a PLL pulse component into two and comparing each of them with each other so as to detect a phase error to a clock signal directly. CONSTITUTION:A phase error detection circuit 4 consists of an analog multiplication circuit 6 and an LPF 7, an output from the LPF 7 is sent to the frequency control terminal of a VCO 8 being a variable frequency oscillation circuit as a phase error signal and an output from the VCO 8 is extracted from an output terminal 9 as a clock signal. Moreover, the output from the VCO 8 is supplied to a phase error detection pulse output circuit 10 and the output pulse from the circuit 10 is fed to an analog multiplier circuit 6. A phase error detection pulse from the circuit 10 is a pulse to detect a phase error with respect to a pulse Pc being a PLL pulse component in a recovered RF signal from an equalizer 3 and has a pulse period nearly equal to the period of the said pulse Pc. |
