发明名称 |
Method for forming aligned interconnections between logic stages |
摘要 |
A layout for random logic in which different stages are assigned to columns according to the flow of logic signal. Each stage may consist of several parallel logic blocks defining a logic function and having an output. The logic blocks are implemented by several diffusion areas, not necessarily contiguous. The output line of a logic block is aligned vertically to match one or more gate electrodes of following stages that it drives. The interconnection to the following stages can be implemented by a single horizontal polysilicon line which also functions as the gate electrodes. The breaks in the diffusion of a logic block can accommodate the passage of polysilicon lines not being used in that logic block.
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申请公布号 |
US4742019(A) |
申请公布日期 |
1988.05.03 |
申请号 |
US19850792997 |
申请日期 |
1985.10.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BECHADE, ROLAND A. |
分类号 |
H01L21/822;H01L21/8234;H01L23/528;H01L27/04;H01L27/088;H01L27/118;(IPC1-7):H01L21/38;H01L21/44 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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