| 摘要 |
PURPOSE:To detect the erroneous operation of an interleave circuit, by distributing the wiring clock of each latch circuit of a latch circuit group. CONSTITUTION:At first, the same number of memory circuits 7A, 7B as the number of the latch circuits 1A, 1B provided to a latch circuit group 1 are provided. The circuits 7A, 7B constituting a memory circuit group 7 store whether writing clocks WCK 1, WCK 2 are applied to the circuits 1A, 1B. Succeedingly, on the basis of the presence of reading clocks PCK 1, PCK 2, it is judged whether a multiplexer 4 reads data from the circuits 1A, 1B having performed latch operation. Next, when memory showing that there is the previous writing order in the circuits 7A, 7B left at the point of time when the clocks WCK 1, WCK 2 are applied, it is cleared that the omission of the clocks PCK 1, 2 is generated in the last time. Therefore, by detecting the memory showing a writing order in the circuits 7A, 7B at each time when the clocks WCK 1, 2 are applied, it can be detected that the omission of the clocks PCK 1, 2 is generated at any point of time by an erroneous operation detecting means 9.
|
