发明名称 TIMING SIGNAL GENERATING CIRCUIT
摘要 <p>PURPOSE:To prevent the operation of other port boards from being affected even if transiently wrong port board information from an extension port board is applied to the titled circuit by sequentially selecting input port board information by an address selecting means driven with the output of a counter, and applying the result to a storage means. CONSTITUTION:The address selecting means 91 which is driven with the output of the counter 92 sequentially selects input port board information; and the address of the selected port board information is applied as the high-order bits to a storage means 93, and the output of a counter 92 is applied as the low-order digit bits to read information of a timing signal out. Then the address selecting means 91 switches the address of the storage means by port boards in order. Consequently, even if port board information is incorrect owing to the extension of a port board, this wrong port board information is not applied to the storage means while another port board is selected, thereby eliminating influence upon the operation of other port boards.</p>
申请公布号 JPS63191431(A) 申请公布日期 1988.08.08
申请号 JP19870023914 申请日期 1987.02.04
申请人 FUJITSU LTD 发明人 WATANABE OSAMU
分类号 H04J3/02;G06F1/04 主分类号 H04J3/02
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