| 摘要 |
<p>A header driven packet switching system including packet header processing circuits (41, 42 ... 4 m) for controlling the routing and header rewriting of data packets. The packet header processing circuits are the hunted type and are arranged independently from incoming lines (11 - 1n) so that the packet switching capacity of the system will be improved, a high speed packet switching realized, and an improved flexibility of the system against traffic congestion will be obtained. In addition, it is possible to arrange the pocket header processing circuits (41, 42 ... 4m) according to traffic conditions.</p> |
