LOGIC CIRCUIT SIMULATION METHOD

摘要

PURPOSE:To curtail the quantity of a memory by eliminating a partial circuit having no relation to a logic circuit operation which is a simulation object. CONSTITUTION:A signal name beginning with an alphabetical character of K is given in advance to a signal related to a scan system logic, as a standard of the time of a logical design. The output signal from an unprocessed element is fetched. elements 31-33 are converted to '&' since output signal names are all signal names beginning with K, and as a result they are eliminated. An element 36 is converted to & since one piece of the outputs is a signal name beginning with K, but it is not eliminated since other signal than & is left as an output signal. elements 34, 35 are not eliminated.