| 摘要 |
PURPOSE:To assure high integration without reducing the capacitance coupling ratio in a memory transistor region by extending a second gate of the memory transistor region to the upper of a gate of another transistor region. CONSTITUTION:A cell in a region L1 is formed of two transistor regions 1, 2 of storage and selection. A first gate 13 of a selection transistor region 2 is formed of a polysilicon film, and part of a first insulating film 8 serves as a tunnel insulating film 7, the former film being formed in contact with the lower part of a second gate 6 of the memory transistor region 1. A floating gate 6 is located extending to the upper of at least part of the selection gate 13. A third gate 14 for controlling the floating gate 6 is formed on the upper of the floating gate 6 via second insulating film 5. The device is formed by a triple layer polysilicon gate process. Such a configuration reduces the width of the floating gate 6 but keeping unchanged the area of the floating gate 6. A separation space 4 between the two transistor regions 1, 2 is reduced and formed by film deposition. |
