| 摘要 |
PURPOSE:To attain the coincidence of switching timing and to eliminate the waveform distortion of an output logic signal by adding a dummy FET and making a circuit into a symmetric structure. CONSTITUTION:The title circuit has plural circuits with a power source 41 common and plural circuits 31a-31c are switched in accordance with the combination of input logic signals D1 and D2. A current is supplied to the power source 41 through the switched circuit and a voltage generated at the load resistance of the switched circuit is outputted as the output logic signal. These plural circuits 31a-31c are respectively equipped with plural steps of FETs 34, 37 and 38 connected in series, the circuit is made a logic circuit in which the number of steps of FETs of at least one circuit is smaller than the number of steps of the other circuits, a dummy FET 35 is added in series to this circuit, the number of steps is made to coincide with the number of steps of the other circuits and when it is switched to the circuit to which the dummy FET 35 is added, the dummy FET is on-operated. Thus, the coincidence of the switching timing can be attained and the waveform distortion of the output logic signal can be eliminated. |
