| 摘要 |
Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs) and related methods are disclosed. A flip-flop circuit latches a representation of a received input data signal in a lower voltage domain, in a latch circuit in a higher voltage domain without need for separate voltage level shifters. As a result, insertion loss/delay is minimized, thereby increasing performance. In certain aspects, the flip-flop circuits employ a gate-controlled, data control transistor to control activation of the latch circuit. By coupling the input data signal to a gate of the data control transistor, the input data signal in the lower voltage domain is not directly latched into the latch circuit. Instead, the data control transistor is configured to activate the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to a clock signal. |
| 主权项 |
1. A flip-flop circuit, comprising:
an input stage in a lower voltage domain, the input stage configured to receive an input data signal on a data input in the lower voltage domain and a clock signal on a clock input; a master stage in a higher voltage domain than the lower voltage domain, the master stage comprising:
a control circuit, comprising:
a clock control transistor comprising: a gate electrode configured to receive the clock signal, a first current electrode, and a second current electrode coupled to a first current electrode of a data control transistor;the data control transistor comprising: a gate electrode coupled to the data input to receive the input data signal, the first current electrode coupled to the second current electrode of the clock control transistor, and a second current electrode; andthe control circuit configured to generate a control signal based on an activation of the clock control transistor by the clock signal and the data control transistor by the input data signal; anda latch circuit comprising a first latch node coupled to the control circuit to receive the control signal, the latch circuit configured to store a latched voltage as a first latched input data in the higher voltage domain, based on the input data signal in response to the control signal from the control circuit; a slave stage in the higher voltage domain, the slave stage configured to receive the first latched input data from the master stage and latch the first latched input data as a second latched output data; and an output stage configured to provide the second latched output data as a flip-flop output. |
