| 发明名称 |
ENERGY EFFICIENT PROCESSOR CORE ARCHITECTURE FOR IMAGE PROCESSOR |
| 摘要 |
An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lanes of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array. |
| 申请公布号 |
US2016313999(A1) |
申请公布日期 |
2016.10.27 |
| 申请号 |
US201514694815 |
申请日期 |
2015.04.23 |
| 申请人 |
Google Inc. |
发明人 |
Meixner Albert;Redgrave Jason Rupert;Shacham Ofer;Finchelstein Daniel Frederic;Zhu Qiuling |
| 分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a program controller to fetch and issue instructions; and, an execution lane having at least one execution unit to execute the instructions, the execution lane being part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lanes of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array. |
| 地址 |
Mountain View CA US |
