发明名称 Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure
摘要 A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.
申请公布号 US2016313980(A1) 申请公布日期 2016.10.27
申请号 US201514694890 申请日期 2015.04.23
申请人 Google Inc. 发明人 Meixner Albert;Shacham Ofer;Patterson David;Finchelstein Daniel Frederic;Zhu Qiuling;Redgrave Jason Rupert
分类号 G06F9/44;G06F9/30 主分类号 G06F9/44
代理机构 代理人
主权项 1. A machine readable storage medium, and not a transitory electronic signal, having program code that when processed by a computing system causes the following method to be performed: instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory, the first reserved region to keep data of an input image array, the second reserved region to keep data of an output image array, wherein, said application software development environment contemplates processing for different array locations of an image array with multiple instances of said virtual processor operating at a different respective array location, each of said virtual processors having said instruction set architecture and said memory model; and, simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.
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