发明名称 TIME MULTIPLEX LOGIC CIRCUIT
摘要 <p>PURPOSE:To improve the efficiency of multiplexing by providing a control section selecting only a buffer memory not in idle and multiplexing a signal from said buffer memory in response to the content of the buffer memory BFM. CONSTITUTION:BFMs 11-14 provided respectively to input ports 1-4 send an idle signal when the content is idle, a control section 31 receives the signal and discriminates it that the relevant BFM is idle by the idle signal and sends a control signal to select only the buffer memory not in idle state to a TPM 21. Thus, when a data exists in all the BFMS 11-14, signals 'A'-'D' are selected by the TPM 12 sequentially and repetitively. When only the BFMs 11, 13 have a data, only the signals 'A', 'C' of the BFMS 11, 13 are selected and no idle signal is caused in the multiplexed signal.</p>
申请公布号 JPH02164158(A) 申请公布日期 1990.06.25
申请号 JP19880318504 申请日期 1988.12.19
申请人 NEC CORP 发明人 NAGARA SHIGENORI
分类号 主分类号
代理机构 代理人
主权项
地址