发明名称 ANAROGU*DEJITARUHENKANKI
摘要 A threshold arrangement includes two complementary transistors whose channels are situated in series between two supply terminals. In order to obtain a substantially square-wave relationship between the output voltage on the common drain electrodes and the input voltage on the interconnected gate electrodes, a direct voltage source is included between the two gate electrodes, which source has a voltage which is preferable substantially equal to the supply voltage minus the sum of the threshold voltages of the two complementary transistors.
申请公布号 JPH0237729(B2) 申请公布日期 1990.08.27
申请号 JP19790057579 申请日期 1979.05.10
申请人 FUIRITSUPUSU FURUUIRANPENFUABURIKEN NV 发明人 KURAUDE YAN PURINSHIPE FUREDERITSUKU RE KAN;MAURISU BINSENTO UERAN;KARERU HARUTO
分类号 H03K17/30;H03K17/693;H03K19/0948;H03M1/00;H03M1/36 主分类号 H03K17/30
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