| 摘要 |
A multiplier circuit comprises two prior art multiplier cells. The problem of different signal transit times in the emitter amplifiers and in the differential steps for the input signals, which must be treated identically, is overcome by arranging the transmission paths symmetrically. The limiting frequency of the arrangement according to the invention is now limited only by the switching time of the bipolar transistors used and not by the phase errors and is therefore higher than in a prior art multiplier circuit. For all frequencies below the limiting frequency, an output signal with a phase difference of 90 DEG lies exactly at the centre of the modulation range. |
