| 摘要 |
An A output and a B output of a register file 16 are each provided to an associated multiplexer (18,20). Each multiplexer has as a further input a bus (CB00:31) that conveys a result from an ALU 22 via an ALU shifter 28. Outputs of the multiplexers are provided to corresponding A or B inputs of the ALU. Each multiplexer is controlled by an associated register file address comparator (24,26). The address comparators each have as an input corresponding register file A and B update and access addresses. The address comparators compare their associated register file update and access addresses to determine if the register file register selected for access is equal to the register file register selected for update. If these two addresses are found to be equal it is indicated that the result of an ALU operation during an instruction cycle N is to be used as an operand for an ALU operation during a cycle N+1. When this condition is detected the output of the associated address comparator enables the corresponding multiplexer select input to gate the ALU result directly to the corresponding input of the ALU, thereby effectively bypassing the register file. |
