发明名称 3D package with through substrate vias
摘要 A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.
申请公布号 US9530759(B2) 申请公布日期 2016.12.27
申请号 US201615090475 申请日期 2016.04.04
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Lii Mirng-Ji;Kuo Hung-Yi;Tsai Hao-Yi;Shih Chao-Wen;Yu Tsung-Yuan;Hsiao Min-Chien
分类号 H01L23/48;H01L23/52;H01L29/40;H01L21/44;H01L21/48;H01L21/50;H01L25/065;H01L23/522;H01L23/31;H01L21/768;H01L21/8234;H01L23/528;H01L23/00;H01L23/498;H01L23/525;H01L21/56 主分类号 H01L23/48
代理机构 Slater Matsil, LLP 代理人 Slater Matsil, LLP
主权项 1. A device comprising: a first integrated circuit die including a transistor formed at a top surface of the first integrated circuit die and a conductive through via extending from the top surface to a bottom surface of the first integrated circuit die; a metallization layer over the top surface of the first integrated circuit die; contact pads disposed over the metallization layer; a protection layer disposed over the contact pads; a first redistribution layer (RDL) disposed over the protection layer and extending to the contact pads through openings in the protection layer; first connectors disposed over/on the first RDL; a molding compound over the first RDL and around the first connectors; a second RDL disposed on the bottom surface of the first integrated circuit die and electrically connected to the conductive through via; and a second integrated circuit die mounted to the bottom surface of the first integrated circuit die and electrically connected to the second RDL.
地址 Hsin-Chu TW