发明名称 |
Test selection techniques |
摘要 |
A test selection system is provided which includes a semiconductor substrate (S) having a pin (AX) connected thereto and an integrated circuit (M) disposed on the substrate (S) and connected to the pin (AX) having an operating voltage within a given voltage range. A latch conditioning circuit (12) having an input responsive to a voltage of a given magnitude has an output (NB) connected to a latch (14), and a voltage control circuit (10) operable at a voltage without the given voltage range selectively applies a control voltage of the given magnitude to the input of the latch conditioning circuit (12). A voltage without the given voltage range is applied to the pin (AX) during a first interval of time to produce the control voltage for establishing a test mode and a voltage within the given voltage range is applied to the pin (AX) during a second interval of time to establish a normal operating mode for the integrated circuit (M). |
申请公布号 |
US5019772(A) |
申请公布日期 |
1991.05.28 |
申请号 |
US19890355589 |
申请日期 |
1989.05.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DREIBELBIS, JEFFREY H.;GABRIC, JOHN A.;HEDBERG, ERIK L. |
分类号 |
G01R31/28;G01R31/317;H01L21/66 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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