发明名称 SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To reduce the memory capacity of a memory circuit by providing a limiter circuit to the signal processing circuit, in which the limiter circuit is connected between an input side of the memory circuit and an input side of a flip-flop circuit, decides whether or not an input data stays in a valid area and outputs the result of decision. CONSTITUTION:Upon the receipt of an input data DI, a memory circuit 1A outputs arithmetic result data corresponding to the input data DI to a flip-flop circuit 3. On the other hand, the input data DI is also inputted to a limiter circuit 4, which decides whether or not the input data DI is resident in a valid area and outputs its result of discrimination f1. Then the arithmetic result data outputted from the circuit 1 and the signal outputted from the circuit 4 and representing the result of decision f1 are inputted to the next stage flip-flop circuit 3, from which a data DO is outputted. Thus, the memory capacity of the memory circuit 1A is enough to be data for the valid area and the memory capacity is reduced to one over several of the memory circuit.
申请公布号 JPH04119007(A) 申请公布日期 1992.04.20
申请号 JP19900237156 申请日期 1990.09.10
申请人 MITSUBISHI ELECTRIC CORP 发明人 YAMASHITA SHINJI
分类号 H04N1/409;G06T5/20;H03H17/00;H03H17/02;H04N1/40 主分类号 H04N1/409
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