| 摘要 |
Parallel low-level and high-level quadrature demodulators (60,62) are provided, each including high speed analog-to-digital converters (82,84) with a nominal number of bits. A signal limiter (56) upstream of the low-level demodulator (60) limits the amplitude of an input analog signal (IF IN) to a value corresponding to a predetermined signal level. An attenuator (58) upstream of the high-level demodulator (62) attenuates the input signal (IF IN) by a predetermined factor, so that the signal level into the high-level demodulator (62) is correspondingly lower than the signal level into the low-level demodulator (60). When the amplitude of the input signal (IF IN) is below a predetermined value, a digital switching and scaling unit (72) selects the output signals from the low-level demodulator (60) and extends the digital output to a larger number of bits. When the amplitude of the input signal (IF IN) is above the value corresponding to the maximum amplitude handling capability of the low-level demodulator (60), the switching and scaling unit (72) selects the output signals from the high-level demodulator (62), amplifies them by the predetermined scaling factor to restore their original amplitude, and extends the digital output to the larger number of bits. Thus, the dynamic range of a single detector is extended by a two-channel parallel detector scheme by a value corresponding to the attenuation/scaling factor used. The demodulators (60,62) may be of the analog or direct-digital-sampling type.
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