| 摘要 |
PURPOSE:To facilitate the high speed evaluation of a microcomputer by provid ing an instruction RAM and an access control circuit which loads and stores the instructions into the instruction RAM. CONSTITUTION:When the CS signal of an access control circuit 9 is active, an effective address generating circuit 6 is activated and a data bus control circuit 7 is connected to only an instruction RAM 8 via a bus. Under such conditions, the replacement of instruction groups is possible between an external memory and the RAM 8 for an evaluating instruction group store memory of the RAM 8. Then the circuit 9 is inactivated by the CS signal, the function of the RAM 8 is activated and the RAM 8 works as if an instruction ROM of an SC microcomputer were available. |
