| 主权项 |
1. A non-volatile memory, comprising:
a substrate; a floating gate transistor, a select transistor and a stress-releasing transistor, disposed on the substrate and coupled in series with each other, wherein the stress-releasing transistor is located between the floating gate transistor and the select transistor, wherein the floating gate transistor comprises:
a floating gate, disposed on the substrate;a first doped region and a second doped region, respectively disposed in the substrate at two sides of the floating gate; anda first dielectric layer, disposed between the floating gate and the substrate; the select transistor comprises:
a select gate, disposed on the substrate;a third doped region and a fourth doped region, respectively disposed in the substrate at two sides of the select gate; anda second dielectric layer, disposed between the select gate and the substrate; the stress-releasing transistor comprises:
a stress-releasing gate, disposed on the substrate;the second doped region and the third doped region, wherein the second doped region is located between the floating gate and the stress-releasing gate, and the third doped region is located between the select gate and the stress-releasing gate; anda third dielectric layer, disposed between the stress-releasing gate and the substrate; at least one first well region, disposed in the substrate, wherein the first doped region to the fourth doped region are located in the at least one first well region; a first capacitor and a second capacitor, wherein the first capacitor, the second capacitor and the floating gate transistor are disposed in separation and are coupled to each other, wherein the first capacitor comprises:
the floating gate;at least one fifth doped region, disposed in the substrate at two sides of the floating gate; anda fourth dielectric layer, disposed between the floating gate and the substrate, the second capacitor comprises:
the floating gate;at least one sixth doped region, disposed in the substrate at the two sides of the floating gate; anda fifth dielectric layer, disposed between the floating gate and the substrate; a second well region, disposed in the substrate, wherein the at least one fifth doped region is located in the second well region; and a third well region, disposed in the substrate, wherein the at least one sixth doped region is located in the third well region. |
