PARALLEL SCRAMBLER IN MULTIPLEXING TRANSMISSION SYSTEM

摘要

The parallel scrambling circuit realizes multiple transmission system by processing transmission signal with high speed by 8-bit units. The circuit includes a series to parallel converter (21) for converting serial input data to 8-bit parallel data, a first latch (22) for latching the 8-bit parallel data, a PN sequence generator (23) for generating 7 PN sequences a decimation sequence generator (24) for generating 8 decimation sequences related to 8-bit parallel data, a scrambling output generator (25) for scrambling the 8-bit parallel data, a second latch (26) for latching the scrambled 8-bit parallel data, and a parallel to series converter (27) for converting 8-bit scrambled data to serial data.