| 摘要 |
PURPOSE:To improve the processing speed of floating point operation by providing a computing element with at least one shift register and making the computing element execute two or more operations such as logical operation, addition/ subtraction and comparation. CONSTITUTION:The contents of registers A, B are inputted to a selecting instruction control circuit 9. A comparator 12 is selected and the most significant bit position (n) of a bit '1' is found out by a register A. The bit position (n) is loaded to a counter circuit 7. The circuit 7 sends a count value (n) to an input control circuit 5 and an output control circuit 6. The count value (n) is sent and stored to/in a control flag. When the control flag CF(n) is not '0', the circuit 9 selects an adder/subtractor 11 and a logical operation circuit 10. The adder/subtractor 11 subtracts the value (n) from the contents of a register B and outputs the subtracted result to the circuit 6. Simultaneously with the operation of the adder/subtractor 11, the circuit 10 shifts the contents of the register A to the left by n bits and outputs the shifted result to the circuit 6. |
