ADDRESS LATCH AND COUNTER CIRCUIT IN VME

摘要

The address generator circuit for transmitting data at a block unit to improve data transmission rate comprises a decoder (2) for receiving a 32 bit address signal and an address modifier code (AM code) from a master (1) of the versa module Europe (VME) bus system to output a block transmission mode signal (BLKMD) and a selecting signal (SLCTED), an address buffer (3) for outputting the uppermost 24 bit address if in block transmission mode and outputting the 32 bit address if not in block transmission mode, and an address latch and counter (4) for receiving the block transmission mode signal, the selecting signal and a lowermost 7 bit address to output a variable output address (OA) according to the input of a longword signal (LWORD) and counter clock (CNTCLK).