Data transmission between two units coupled to common memory - using logic control unit built into one unit to generate enable signals controlling access

摘要

Data transmission is provided between two units (1,2) that have access to the same data buffer (3). One of the units (2) has a serial data input and produces byte parallel data transfer to the memory control logic. The control logic stage has connections to a data latch, address control stages, and memory control stages. The operating cycle is defined by two valid timing regions. Memory request signals are generated and the control logic responds to generate the appropriate access signals. ADVANTAGE - Allows considerable variations in data transmission conditions. Both units can operate under independent clock frequencies.