| 摘要 |
The circuit comprises (a) an input terminal for receiving video signal, (b) a synchronising signal separator for separating the synchronising signal from the video signal, (c) a standard clock pulse generator for generating a standard clock pulse generator for generating a standard clock pulse train, (d) an even/odd field detector detecting whether the video signal is of an even or odd field according to the separated synchronizing signals, (e) a synchronizing pattern generator responding to the detected results of the even/odd field detector, (f) a composite synchronizing signal generator generating composite synchronizing signals, and (g) an adder adding the composite synchronizing signal generated by the composite synchronizing signal generator to the video signal.
|
