| 摘要 |
A programmable compensated digital delay circuit is described in a design format that is suited for integrated circuitry utilizing complementary MOS technology. In the integrated circuit delay, a precise single element is provided that spans a wide delay range. The element has multiple time delay cells that are selectively interconnectable to form one or more delay lines. Each time delay cell has controllable capacitive elements and current sources which, in turn, are selected by use of a nonvolatile memory. Both the capacitive elements and the current sources are arrayed in a binary weighted manner. The delay is set by using portions of the memory to select capacitive elements and current sources. With the memory functioning with other integrated circuitry, different capacitive elements and current sources are switched into and out of the circuit. The programmable compensated digital delay circuit of the invention is self-compensating for temperature and power supply variations. The compensation adjusts the operating levels and subranges of the time delay lines. A precision delay line is formed from complementary MOS technology without using a reference frequency. The precision delay line is further characterized by high pulse fidelity that is, one with substantially no pulse width distortion and by high operating frequency.
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