主权项 |
1. An integrated circuit comprising:
A. a test clock lead, a data register enable lead, and a test mode select lead; B. a state machine having a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, and data register control outputs; C. command flip flop circuitry having a clock input coupled to the test clock lead, an input coupled to the test mode select lead, and a command flip flop circuitry output; D. first data register circuitry having first data register control inputs; E. second data register circuitry having second data register control inputs separate from the first data register control inputs; and F. dual port router circuitry including:
(i) a first routing circuit having an input connected to the data register control outputs, an input connected to the command flip flop circuitry output, a data register enable input connected to the data register enable lead, and an output connected to the first data register control inputs; and(i) a second routing circuit having an input connected to the data register control outputs, an input connected to the command flip flop circuitry output, a data register enable input connected to the data register enable lead, and an output connected to the second data register control inputs. |