Harmonic lock detector.

摘要

A circuit for detecting harmonic lock of a phase-locked loop includes a frequency synthesizer (12) for receiving a reference clock signal and for generating an oscillator clock signal. A phase generator (26) receives the reference clock signal and generates a phase of the reference clock signal. A shift register (18) receives as an input the oscillator clock signal and is clocked by the phase of the reference clock signal to produce an output that is a repetitive sequence of logic states. A harmonic decode circuit (28) decodes the shift register output to determine which harmonic the phase-locked loop has locked onto.