发明名称 |
Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals. |
摘要 |
<p>A synchronous dynamic random access memory device latches external command signals for defining the internal sequence, and an input circuit (1) produces an internal control signal (CTL1) from a system clock signal (CLK) and a clock enable signal (CKE) for latching the external command signals, wherein the input circuit maintains the internal control signal in an active level for a predetermined time period regardless of the duty ratio of the external clock signal so that a malfunction hardly takes place. <IMAGE></p> |
申请公布号 |
EP0623931(A2) |
申请公布日期 |
1994.11.09 |
申请号 |
EP19940105058 |
申请日期 |
1994.03.30 |
申请人 |
NEC CORPORATION |
发明人 |
OBARA, TAKASHI, C/O NEC CORPORATION |
分类号 |
G11C11/407;G11C11/417;G11C11/4076;(IPC1-7):G11C11/407 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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