INTERRUPT CONTROLLER FOR AN INTEGRATED CIRCUIT

摘要

A programmable microprocessor control system includes a microprocessor in bus communication with a plurality integrated of circuit modules (ASIC) one of which integrated circuit modules is a interrupt controller. The microprocessor is also in bus communication with memory units. Each of the integrated circuit modules generates a plurality of control signal in response to data placed on the bus by the microprocessor in response to the programming of microprocessor and also generates one or more of a plurality of interrupt signals of one or more of a plurality of status types (INTR-0 through INTR-7), the interrupts representing a respective status of the source circuit module. The interrupt controller includes a first group of programmable registers for enabling respective one of the interrupts (INTR0-INTR7) for each of the respective source circuit modules and generating a respective masked interrupt signal (IMR(1)-IMR(6) of that type upon receiving an interrupt signal of that type from any one of source circuit modules. A prioritizing circuit is provided for receiving the masked interrupt signal (IMR(1)-IMR(6) generating one of a plurality of priority interrupt signal (IP1-IP3) in response to receiving a respective one of the masked interrupt signal (IMR(1)-IMR(6) wherein the number of priority interrupt signal (IP1-IP3) is less than the number of masked interrupt signals (IMR(1)-IMR(6).