| 摘要 |
A semiconductor integrated logic circuit making it feasible to perform different testing methods including a scan path test method while retaining a minimized number of an excluseive external terminal for testing. A first internal logic circuit comprises first flip-flop circuits which operate either in a logic operation mode or in a shift register operation mode through an operation mode control signal. At least one second flip-flop circuit is connected to the input side of the first internal logic circuit, which does not participate in the logic operation of the first internal logic circuit and can operate as a shift register together with the first flip-flop circuits. A second internal logic circuit receives the control signal and the output signal of the second flip-flop circuit and performs a predetermined logic such as an OR logic between the signals to thereby generate and output a testing control signal. |
