发明名称 Display pipe statistics calculation for video encoder
摘要 In an embodiment, a system includes a display processing unit configured to process a video sequence for a target display. In some embodiments, the display processing unit is configured to composite the frames from frames of the video sequence and one or more other image sources. The display processing unit may be configured to write the processed/composited frames to memory, and may also be configured to generate statistics over the frame data, where the generated statistics are usable to encode the frame in a video encoder. The display processing unit may be configured to write the generated statistics to memory, and the video encoder may be configured to read the statistics and the frames. The video encoder may be configured to encode the frame responsive to the statistics.
申请公布号 US9472168(B2) 申请公布日期 2016.10.18
申请号 US201414201421 申请日期 2014.03.07
申请人 Apple Inc. 发明人 Holland Peter F.;Cote Guy;Rygh Mark P.
分类号 G09G5/39;G09G5/00;G09G5/36;G09G5/02 主分类号 G09G5/39
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. ;Merkel Lawrence J.
主权项 1. A system comprising: a display processing circuit configured to generate frames of a video sequence, wherein the display processing circuit is further configured to generate one or more statistics over image data in the frames, wherein the one or more statistics are used by a video encoder to aid in encoding the frames, and wherein the one or more statistics are in addition to the image data; a memory controller coupled to the display processing circuit and configured to couple to a memory through the memory controller, wherein the display processing circuit is configured to write the frames to the memory through the memory controller and further configured to write the one or more statistics to the memory through the memory controller; and the video encoder coupled to the memory controller, wherein the video encoder is configured to read the one or more statistics and the frames from memory and to encode the video sequence responsive to the one or more statistics, and wherein the display processing circuit is configured to transmit a first interrupt to the video encoder responsive to writing the one or more statistics to the memory for a first frame, and wherein the video encoder is configured to read the one or more statistics to prepare for the first frame prior to reading the image data of the first frame, and wherein the display processing circuit is configured to transmit a second interrupt to the video encoder responsive to writing at least a portion of the image data of the first frame to the memory, and wherein the video encoder is configure to read at least the portion of the image data in response to the second interrupt, and wherein the second interrupt is transmitted subsequent to the first interrupt and the video encoder is prepared to encode the first frame by processing the statistics in response to the first interrupt.
地址 Cupertino CA US