发明名称 Apparatus and method for decoding fixed and variable length encoded data
摘要 Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing-an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources-a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.
申请公布号 US5452101(A) 申请公布日期 1995.09.19
申请号 US19920989602 申请日期 1992.12.11
申请人 INTEL CORPORATION 发明人 KEITH, MICHAEL
分类号 G06F9/30;G06F9/38;(IPC1-7):H04N1/41 主分类号 G06F9/30
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