ERROR DETECT & CORRECTION METHOD OF WIDE DATA TRANSMITION

摘要

FIFO buffers for transmitting data to be connected in parallel with each other; an error detector for detecting the errors to compare a filling error signal with an empty error signal, and the generated error amount on the basis of generating time of the filling and empty error signals, a clock for generating the record and read control signals of the FIFO buffers; and a error corrector for generating the filling and empty error correction signals and correcting the above referred errors of the respective flags. The circuit can efficiently detect and correct the errors.