| 摘要 |
<p>A processor is connected to a bus interface unit through a CPU local bus. A memory control unit and an input/output (I/O) control unit are also connected to the CPU local bus. The memory control unit and I/O control unit interface to a memory space and an I/O space, respectively. The bus interface unit provides an interface to an external bus, such as a PCI bus. When the processor initiates a given local bus cycle, the microprocessor asserts an address on the address bus and also asserts an address strobe signal ADS to signal the start of a local bus cycle. After the address becomes stable, decode logic within the memory control unit and the I/O control unit determines whether the address is directed to the memory or I/O address space, respectively. If so, the respective control unit asserts a hit signal to inform the bus interface unit that the current cycle is destined for a device residing on the CPU local bus, and thus that the bus interface unit should not begin an external PCI bus cycle. If, on the otherhand, the address is determined not to be directed to the memory or I/O address space, the respective control unit does not assert the hit signal. Thus, since the hit signal is not asserted, the bus interface unit initiates a corresponding cycle on the external PCI bus to access the PCI slave device. <IMAGE></p> |
