| 摘要 |
<p>The counter comprises an input terminal for receiving the input, a toggle signal generating circuit for generating a periodic toggle signal to mark the number of periods, and a number of n counter cell circuits for effecting the counting in n bits. Each counter cell circuit generates at least a respective bit output, a respective toggle output, and respective carry output. The counter cell circuits are arranged in hierarchical order from a least-significant counter cell circuit to a most-significant counter cell circuit. Each of the respective counter cell circuits is coupled with the next-most-significant counter cell circuit and provides the respective toggle output to the next-most-significant counter cell circuit as a respective toggle input, provides the respective carry/output to the next most-significant counter cell circuit as the respective carry input, except the most-significant counter cell circuit n receives its respective toggle input from the respective carry output of the twice-less-significant counter cell circuit cell circuit n-2.</p> |
