| 摘要 |
An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines (10, 12, 16, 44, 48, 54). Wiring segments (18, 20, 22, 24) run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates (26, 30, 38, 62) and can be efficiently configured into a memory structure and/or logic device.
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