| 主权项 |
1. An image data receiving device comprising:
1st to Kth lane reproduction circuits, where K is an integer of two or greater; 1st to Kth timing adjustment circuits; 1st to Kth lane reproduction outputs; and 1st to (K−1)th selectors, if letting N be a positive integer smaller than K and n be a positive integer, the Nth lane reproduction circuit transmitting data of an nth pixel, the (N+1)th lane reproduction circuit transmitting data of an (n+1)th pixel adjacent to the nth pixel, the Nth timing adjustment circuit having an input terminal electrically connected to the Nth lane reproduction circuit, the (N+1)th timing adjustment circuit having an input terminal electrically connected to the (N+1)th lane reproduction circuit, the Nth lane reproduction output being able to be electrically connected to an output terminal of the Nth timing adjustment circuit, and the Nth selector being able to electrically connect one of the output terminal of the Nth timing adjustment circuit and the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output. |
