Integrated circuit memory device with balancing circuit including following amplifier coupled to bit line

摘要

In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit constituted as follows: a differential amplifier, means for the precharging of the bit line before a reading phase and means for the balancing of the input potentials of the differential amplifier before the reading phase. The balancing means comprise a follower amplifier that has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current of the bit line in a direction tending to cancel the output voltage to the differential amplifier. A cascode transistor can be used to accelerate the reading.