| 摘要 |
A sense amplifier circuit includes a voltage developing stage which receives first and second data inputs, din1 and din2, and generates a differential voltage, in response to feedback signals received from a first and second data outputs, dout1 and dour2, of the sense amplifier circuit, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a full-swing locking stage which generates and latches, in response to a control signal PHI 2', complementary latched data outputs from the first and second data outputs, dout1 and dout2, generated by the voltage developing stage; and a voltage equalization stage which equalizes, in response to a control signal PHI 0', voltages on data lines respectively connected to the first and second data outputs, dout1 and dout2. In addition, the voltage equalization stage is used to initiate the voltage developing stage. Timing of the control signals, PHI 0' and PHI 2', is such that the control signal PHI 2' is activated after a finite period following the deactivation of the second control signal PHI 0'. To minimize power consumption of the sense amplifier circuit, the control signal PHI 0' is deactivated when either the voltage developing or full-swing locking stage is in operation and the voltage equalization stage is not needed.
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