发明名称 Memory control apparatus permitting concurrent access by compressing addressing time window and multiplexing
摘要 A memory control apparatus that compresses the time widths of time slots of addresses sequentially outputted from a data processing unit so as to access a memory. Readout data is transferred to the data processing unit while expanding the time slot. In a vacant time formed by compressing the time widths of the time slots of the addresses from the data processing unit, refresh processing or hard disk transfer processing is executed. The time widths of the time slots of addresses sequentially outputted from a CPU are compressed so as to write data in the memory, and parallel to this operation, refresh processing can be executed in a vacant time. The memory control apparatus is suitably used in accesses of waveform data between a tone generator system and a waveform memory. Waveform data supplied from another unit can be written in the waveform memory parallel to tone generation using all tone generation channels of the tone generator system for tone generation.
申请公布号 US5559994(A) 申请公布日期 1996.09.24
申请号 US19950461168 申请日期 1995.06.05
申请人 YAMAHA CORPORATION 发明人 ANDO, TOKIHARU
分类号 G06F12/02;G06F12/00;G06F13/16;G10H7/02;G11C7/00;G11C27/00;(IPC1-7):G06F13/16 主分类号 G06F12/02
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