| 摘要 |
a clock generating means(1) generating the reference clock(CLK); a latch clock generating means(13) generating latch clocks(LCK1,LCK2) according as operating a coefficient clock(CCK) and a latch clock(LCLK); a horizontal address generating means(2) generating a horizontal address(HAddr) and the synchronization signal(Vsyn) of 1H period; a vertical address generating means(3) generating the vertical address(VAddr); a data storing means(4) outputting the compensated data; a latch means(15) latching the output of the data storing means according to the latch clock(LCK1); a field reading means(12) outputting a switching signal(S1); a digital/analog converter(5) converting the output of a latch means(17) to an analog; and an amplifying means(7) outputting the output of a low pass filter(6) to a yoke coil(YC) after amplifying.
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