| 摘要 |
In a high speed digital computer data transfer system, a data bus driver, implemented using complementary metal-oxide-semiconductor (CMOS), reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Voltage overshoot and undershoot of the reduced bus logic levels are prevented by two "clamping diode" transistors. One of the two clamping diodes connected to the data bus is biased to a point just below conductivity, while the second clamping diode is biased to a point just below conductivity. As a result, if the output voltage rises above a selected level, the first clamping transistor acts as a conducting diode to pull the output voltage down, and, in a similar manner, if the output voltage at node falls below a selected level, then the second clamping transistor functions as a conducting diode to pull the output voltage up to an acceptable level.
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