Solid-state image pickup apparatus, signal processing method for a solid-state image pickup apparatus, and electronic apparatus

摘要

A solid-state imaging device includes a pixel array section that has at least one pixel with a photoelectric conversion unit and a charge detection unit. A driving section is configured to read out a signal of the pixel, a first portion of said signal being based on signal charge, a second portion of said signal being based on a reset potential. A signal processing section is configured to read out the first portion of the signal as a reference voltage, with the reference voltage being adjusted to cause the first and second portions of the signal to be within an input voltage range.

主权项

1. An imaging device comprising:
a pixel configured to output a pixel signal; a signal line configured to read out the pixel signal; and a comparator including:
first and second differential transistors,a first capacitor disposed between a gate of the first differential transistor and a reference signal generation section configured to supply a reference signal,a second capacitor disposed between a gate of the second differential transistor and the signal line,a first circuit including a third transistor and a fourth transistor, one of a source or a drain of the third transistor being coupled to the gate of the first differential transistor, the other of the source or the drain of the third transistor being coupled to one of a source or a drain of the fourth transistor, and the other of the source or the drain of the fourth transistor being coupled to a first line supplied with a predetermined voltage, anda second circuit including a fifth transistor and a sixth transistor, one of a source or a drain of the fifth transistor being coupled to the gate of the second differential transistor, the other of the source or the drain of the fifth transistor being coupled to one of a source or a drain of the sixth transistor, and the other of the source or the drain of the sixth transistor being coupled to the first line, wherein a drain or a source of the first differential transistor and a drain or a source of the second differential transistor are coupled to a second line supplied with a power supply voltage, and wherein the power supply voltage is different from the predetermined voltage.